• CPU configuration

• 1K×13 bits on-chip Flash memory
• 48×8 bits on-chip registers (SRAM)
• 8-level stacks for subroutine nesting
• 3 programmable Level Voltage Reset LVR : 4.0V, 3.5V, 2.7V
• Less than 1.5 mA at 5V / 4 MHz
• Typically 20 μA, at 3V / 32kHz
• Typically 1.5 μA, during sleep mode

• I/O port configuration

• 4 bidirectional I/O ports: P5, P6 and P8
• 14 I/O pins
• Wake-up port : P6
• High sink port : P6
• 6 programmable pull-high I/O pins
• 5 programmable pull-down I/O pins
• 6 programmable open-drain I/O pins
• External interrupt with Wake-up : P60

• Operating voltage range

• 2.4V~5.5V at -40°C~85°C (Industrial)
• 2.2V~5.5V at 0°C~70°C (Commercial)

• Operating frequency range (base on two clocks)

• Crystal mode : DC~16MHz @ 4.5V~5.5V ;

DC~8MHz @ 3V~5.5V ; DC~4MHz @ 2.2V~5.5V

• ERC mode : DC~16MHz @ 4.5V~5.5V ;

DC~8MHz @ 3V~5.5V ; DC~4MHz @ 2.2V~5.5V

• IRC mode : DC~16MHz @ 4.5V~5.5V ;

DC~4MHz @ 2.2V~5.5V Drift Ra

Internal RC  Frequency	Drift Rate
	Temperature (-40°C~85°C)	Voltage (2.4V~5.5V)	Process	Total
4MHz	± 3%	± 5%	± 2.5%	± 10.5%
16MHz	± 3%	± 5%	± 2.5%	± 10.5%
8MHz	± 3%	± 5%	± 2.5%	± 10.5%

• Five available interrupts

• Internal interrupt : 2
• External interrupt : 3

• One set of comparator (offset voltage: smaller than 5 mV)
• One 8-bit Timer/Counter

• TC3 : Timer/Counter/PDO (programmable divider output)/PWM (pulse width modulation)

• Peripheral configuration

• 8-bit real timer clock only (TCC) with overflow interrupt
• External interrupt input pin
• 2/4/8/16 clocks per instruction cycle selected by code option
• Power down (Sleep) mode
• High EFT immunity

• Single instruction cycle commands
• Special Features

• Programmable free running Watchdog Timer
• Power-on voltage detector available (2.0V ~ 2.1V)

• Package Type:

• 10-pin MSOP 118mil : EM78F541NMS10J/S
• 16-pin DIP 300mil : EM78F541NAD16J/S
• 16-pin SOP 150mil : EM78F541NASO16AJ/S